1. Field of the Invention
The present invention pertains to a method and a system for managing the voltage on the DC bus of a speed controller for an AC electric motor linked to a current distribution network, the said controller operating according to a voltage control law of U/F type.
2. Description of the Prior Art
In a known manner, a conventional speed controller for an electric motor comprises a DC bus linking the electric motor to the electrical current distribution network. This DC bus carries in particular a rectifier bridge with diodes, a filter with capacitor and an inverter bridge with transistors and diodes.
During normal operation, the electrical energy is transferred from the current distribution network to the electric motor. However, in certain situations, the energy of the motor may be regenerated to the capacitor of the DC bus. These situations are the following:                excessive and overly rapid braking of the motor (deceleration time overly short or braking torque overly high),        at constant speed of the motor, driving of the motor by the load,        outage of the current distribution network.        
In these particular situations, the capacitor of the DC bus may be subject to overvoltages apt to damage it.
In the state of the art, these various situations are managed in the following manner:
With reference to FIG. 2, in a conventional speed controller operating according to a control law of vector type there are generally a speed loop and a current loop. A reference frequency Wref is imposed as input and is compared with an estimated frequency West obtained as output. The difference between the two frequencies is amplified by a speed regulator providing as output a current reference Iqref. The difference between the current reference Iqref and the value of the current Iq measured on the motor is amplified by a current regulator to provide the estimated frequency West. The control frequency Wstat dispatched to the stator of the motor is the sum of the estimated frequency West and of the slip compensation Wslip.
In the situations described above, in order to protect the capacitor from overvoltages, a voltage regulating circuit C is used. This voltage regulating circuit C compares first of all the value of the voltage Vbus measured on the DC bus with a determined limit value Vlim. This limit value corresponds to the value above which the capacitor of the DC bus experiences overvoltages apt to damage it.
In case of excessive braking of the motor, the output of the voltage regulating circuit C decreases the current reference Iqref in such a way as to reduce the current returned by the motor to the DC bus and to contrive matters in such a way that the voltage Vbus measured on the DC bus to return to a value below the limit value Vlim.
When the motor is driven by the load at constant speed, the voltage regulating circuit C increases the current reference Iqref in such a way as to increase the estimated frequency West and the speed of the motor and thus limit the voltage on the DC bus.
In case of outage of current on the distribution network, the limit value Vlim is lowered and the voltage regulating circuit C then imposes a current reference Iqref suitable for making the motor decelerate slowly while optimizing the consumption of the available current.
In a speed controller operating according to a nonvector voltage control law of U/F type as presented hereinabove, no current loop or speed loop is tolerated. Such a speed controller is admittedly less effectual but proves to be much more robust and may in particular be used in products such as transformers or fans.
In case of excessive braking of the motor, it is known through patent application JP 56066189 to manage the voltage on the DC bus of a speed controller to protect the capacitor of the DC bus. A comparator is charged with comparing the value of the voltage measured at the terminals of the capacitor with a limit value. When the value of the voltage measured at the terminals of the capacitor is greater than a limit value, the output signal of the comparator instructs the interruption of deceleration. The frequency of the stator is therefore maintained at a constant value. When the value of the voltage tapped across the terminals of the capacitor again becomes less than the limit value, the comparator no longer acts on the frequency and the latter may again decrease according to a ramp having a slope of determined value. Such a device makes it possible to limit the overvoltages experienced by the capacitor of the DC bus during excessive braking. However, after the action of the comparator on the ramp, the resumption of deceleration takes place directly following the nominal slope of the deceleration ramp. The deceleration of the motor therefore occurs with successive jerks that are apt to eventually degrade the operation of the motor.